From the course: Getting Started with RISC-V
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Modularity of the RISC-V ISA - Raspberry Pi Tutorial
From the course: Getting Started with RISC-V
Modularity of the RISC-V ISA
- [Narrator] Now that we have discussed the features that set RISC apart from SISC, it's time to get specific on the RISC-V instruction set architecture. In this sequence, you will see how RISC-V stands alone as today's evolution of the 1980s RISC, following all its original ideas and how it differs from the ARM architecture. First, let me introduce the concept of incremental ISAs, like that in the ARM Cortex-M family. In an incremental ISA, a new processor model must support not only its new ISA extensions, but also all extensions from the previous less capable processors it extends. The purpose of this is to maintain backward compatibility. For example, a low end ISA named A may have a modest instruction set to perform general purpose computing. Then a more advanced Model B may support an incremental set of instructions for more advanced operations. And a third processor model C could add digital signal processing…
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